The need for more functions in a single device has led to die stacking architecture. Although the number of die increases further to accommodate package functionality, the overall package dimensions have not increased; they have stayed the same or decreased (roughly 1.4mm). If this trend continues, in order to keep the same package height, alternate stacking structures need to be investigated. One such opportunity is the spacerless die stacking architecture. Using dummy silicon spacers add to the cost of a package and do not increase the memory or functionality, although they serve as enablers for wire bonding of same size die. Spacerless architecture reduces the package height by eliminating spacers or dummy die. This allows for an increased number of active die to be stacked directly on one another without changing the overall package height, or in some cases reducing the package height. Previous work [1] has been done to develop a steady-state heat conduction model in a two-layer body. This analytical model will be extended to the current multi-layered generic spacerless three dimensional packages (3DP) enabling the computation of temperature for uniform or non-uniform powered die. The computation will account for the contact resistance created by the die attach and the solder balls. Finally validation of this analytically developed model will be carried out with a numerical model.

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