Double data rate (DDR) signaling is widely used in electrical interconnects to eliminate clock recovery and to double communication bandwidth. This paper describes the design of a parallel optical transceiver integrated circuit (IC) that uses source-synchronous, DDR optical signaling. On the transmit side, two 8-bit electrical inputs are multiplexed, encoded and sent over two high-speed optical links. On the receive side, the procedure is reversed to produce two 8-bit electrical outputs. Our IC integrates analog Vertical Cavity Surface Emitting Lasers (VCSEL), drivers and optical receivers with digital DDR multiplexing, serialization, and deserializaton circuits. It was fabricated in a 0.5-micron Silicon-on-Sapphire (SOS) CMOS process. Linear arrays of quad VCSELs and photodetectors were attached to our transceiver IC using flip-chip bonding. A free-space optical link system was constructed to demonstrate correct IC functionality. The test results show successful transceiver operation at a data rate of 500 Mbps with a 250 MHz DDR clock, achieving a gigabit of aggregate bandwidth. While our DDR scheme is well suited for low-skew fiber-ribbon, free-space and waveguide optical links, it can also be extended to links with higher skew with the addition of skew-compensation circuitry. To our knowledge, this is the first demonstration of parallel optical transceivers that use source-synchronous DDR signaling.
- Electronic and Photonic Packaging Division
Source Synchronous Double Data Rate (DDR) Parallel Optical Interconnects
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Gui, P, Kiamilev, F, Wang, X, McFadden, M, Kuznia, C, Ekman, J, Deroba, J, & Haney, M. "Source Synchronous Double Data Rate (DDR) Parallel Optical Interconnects." Proceedings of the ASME 2003 International Electronic Packaging Technical Conference and Exhibition. 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1. Maui, Hawaii, USA. July 6–11, 2003. pp. 655-663. ASME. https://doi.org/10.1115/IPACK2003-35202
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