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Proceedings Papers

Improvement of the Reliability of Thin-Film Interconnections Based on the Control of the Crystallinity of the Thin Films

Osamu Asai, Ryosuke Furuya, Chuanhong Fan, Ken Suzuki, Hideo Miura

Proc. ASME. InterPACK2013, Volume 1: Advanced Packaging; Emerging Technologies; Modeling and Simulation; Multi-Physics Based Reliability; MEMS and NEMS; Materials and Processes, V001T07A006, July 16–18, 2013

Paper No: IPACK2013-73149

DOI: https://doi.org/10.1115/IPACK2013-73149

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Topics: Reliability, Thin films, Electroplating, Copper, Annealing, Current density, Electrical properties, Electron backscatter diffraction, Electrical resistivity, Grain boundaries

Proceedings Papers

Evaluation of the Crystallographic Quality of Electroplated Copper Thin-Film Interconnection Embedded in a Si Substrate

Ryosuke Furuya, Osamu Asai, Chuanhong Fan, Ken Suzuki, Hideo Miura

Paper No: IPACK2013-73148

DOI: https://doi.org/10.1115/IPACK2013-73148

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Topics: Copper, Thin films, Electroplating, Electrical properties, Electrical resistivity, Annealing, Bulk solids, Density, Grain boundaries, High temperature

Proceedings Papers

Effect of Crystallographic Quality of Grain Boundaries on Both Mechanical and Electrical Properties of Electroplated Copper Thin Film Interconnections

Naokazu Murata, Naoki Saito, Kinji Tamakawa, Ken Suzuki, Hideo Miura

Proc. ASME. InterPACK2011, ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 2, 677-684, July 6–8, 2011

Paper No: IPACK2011-52048

DOI: https://doi.org/10.1115/IPACK2011-52048

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Topics: Copper, Electrical properties, Grain boundaries, Thin films, Fracture (Materials), Annealing, Reliability, Brittle fracture, Electron backscatter diffraction, Stress

Proceedings Papers

Stress-Induced and Electro-Migration of Electroplated Copper Thin Film Interconnections Used for 3D Integration

Naoki Saito, Naokazu Murata, Kinji Tamakawa, Ken Suzuki, Hideo Miura

Paper No: IPACK2011-52058

DOI: https://doi.org/10.1115/IPACK2011-52058

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Topics: Copper, Electrodiffusion, Stress, Thin films, Atoms, Sulfur, Current density, Electroplating, Fracture (Materials), Fracture (Process)

Proceedings Papers

Micro Texture Dependence of Mechanical Properties of Electroplated Copper Thin Films Used for Thin Film Interconnection

Naokazu Murata, Kinji Tamakawa, Ken Suzuki, Hideo Miura

Proc. ASME. InterPACK2009, ASME 2009 InterPACK Conference, Volume 1, 353-359, July 19–23, 2009

Paper No: InterPACK2009-89079

DOI: https://doi.org/10.1115/InterPACK2009-89079

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Topics: Copper, Mechanical properties, Texture (Materials), Thin films, Fracture (Materials), Fatigue strength, Grain boundaries, Brittle fracture, Ductile fracture, Fatigue testing

Proceedings Papers

High-Density Room-Temperature 3D Chip-Stacking Using Mechanical Caulking With Compliant Bump and Through-Hole-Electrode

Naoya Watanabe, Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Tanemasa Asano

Proc. ASME. InterPACK2009, ASME 2009 InterPACK Conference, Volume 1, 33-38, July 19–23, 2009

Paper No: InterPACK2009-89274

DOI: https://doi.org/10.1115/InterPACK2009-89274

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Topics: Density, Electrodes, Temperature, Electroplating, Pattern formation

Proceedings Papers

Micro Texture-Induced Variation of Mechanical Properties of Electroplated Copper Thin Films

Muneyuki Otani, Kazuhiko Sakutani, Kinji Tamakawa, Ken Suzuki, Hideo Miura

Proc. ASME. InterPACK2007, ASME 2007 InterPACK Conference, Volume 2, 735-741, July 8–12, 2007

Paper No: IPACK2007-33261

DOI: https://doi.org/10.1115/IPACK2007-33261

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Topics: Copper, Mechanical properties, Texture (Materials), Thin films, Young's modulus, Bulk solids, Grain boundaries, Cold rolling, Deformation, Elasticity

Proceedings Papers

Intermetallic Effects of Electroplated Lead-Free Solder Bumps Using a Novel Single Chamber Electroplating Process for Large Diameter Wafers

J. Teye Brown, Ajay M. Popat, Chad B. O’Neal, Yixiang Xie

Proc. ASME. InterPACK2007, ASME 2007 InterPACK Conference, Volume 2, 743-748, July 8–12, 2007

Paper No: IPACK2007-33906

DOI: https://doi.org/10.1115/IPACK2007-33906

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Topics: Electroplating, Intermetallic compounds, Lead-free solders, Semiconductor wafers, Solders, Alloys, Polishing, Cross section (Physics), Electrons, Flux (Metallurgy)

Proceedings Papers

A Paradigm Shift in the Development of Chemical Mechanical Polishing (CMP): Cost-Effective CMP Planarization in Next Generation Substrate/Package Design and Manufacturing

Stefanie Lotz, Robert Baresel, Dipto Thakurta, Lei Jiang, Tuhin Ghosh

Proc. ASME. InterPACK2005, Advances in Electronic Packaging, Parts A, B, and C, 1031-1036, July 17–22, 2005

Paper No: IPACK2005-73371

DOI: https://doi.org/10.1115/IPACK2005-73371

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Topics: Design, Manufacturing, Polishing, Slurries, Copper, Recycling, Computer-aided design, Data collection, Density, Electroplating

Proceedings Papers

A Chip-Scale Cooling Scheme With Integrated Heat Sink and Thermal-Fluidic I/O Interconnects

Bing Dang, Paul J. Joseph, Xiaojin Wei, Muhannad S. Bakir, Paul A. Kohl, Yogendra K. Joshi, James D. Meindl

Proc. ASME. InterPACK2005, Advances in Electronic Packaging, Parts A, B, and C, 605-610, July 17–22, 2005

Paper No: IPACK2005-73416

DOI: https://doi.org/10.1115/IPACK2005-73416

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Topics: Cooling, Heat sinks, Microfluidics, Silicon chips, Complementary metal oxide semiconductors, Density, Electroplating, Engineering prototypes, Flip-chip, Flip-chip assemblies

Proceedings Papers

SOP Embedded Thin Film Resistors on High and Low Loss Thin Film Dielectrics

Swapan Bhattacharya, Mahesh Varadarajan, Premjeet Chahal, K. J. Lee, Ajanta Bhattacharjee, Rao R. Tummala, Suresh Sitaraman, John Papapolymerou, Manos Tentzeris, Joy Laskar

Proc. ASME. InterPACK2005, Advances in Electronic Packaging, Parts A, B, and C, 1999-2004, July 17–22, 2005

Paper No: IPACK2005-73500

DOI: https://doi.org/10.1115/IPACK2005-73500

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Topics: Dielectric materials, Resistors, Thin films, Alloys, Electroless plating, Adhesion, Copper, Density, Electrical wires, Electroplating

Proceedings Papers

Wafer-Level Packaging Technology With Through-Hole Interconnections in Silicon Substrate

Satoshi Yamamoto, Masanobu Saruta, Hideyuki Wada, Michikazu Tomita, Tatsuo Suemasu

Proc. ASME. InterPACK2005, Advances in Electronic Packaging, Parts A, B, and C, 757-760, July 17–22, 2005

Paper No: IPACK2005-73298

DOI: https://doi.org/10.1115/IPACK2005-73298

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Topics: Packaging, Semiconductor wafers, Silicon, Reliability, Sensors, Alloys, Copper, Density, Electrical resistance, Electroplating

Proceedings Papers

Evaluation of Surface Finish on Build Up Substrate

L. Y. Hung, Y. P. Wang, C. S. Hsiao

Proc. ASME. InterPACK2003, 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2, 839-843, July 6–11, 2003

Paper No: IPACK2003-35153

DOI: https://doi.org/10.1115/IPACK2003-35153

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Topics: Finishes, High temperature, Intermetallic compounds, Nickel, Storage, Plating, Solder joints, Shear (Mechanics), Ball-Grid-Array packaging, Electrons

Proceedings Papers

V-PAC: Vertical Packaging for Assembly-Compatible Chip Stacks

Vincent Malba, Leland B. Evans, Christopher D. Harvey, Anthony F. Bernhardt

Proc. ASME. InterPACK2003, 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2, 853-858, July 6–11, 2003

Paper No: IPACK2003-35194

DOI: https://doi.org/10.1115/IPACK2003-35194

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Topics: Manufacturing, Packaging, Adhesives, Density, Electroplating, Epoxy adhesives, Epoxy resins, Flexible electronics, High temperature, Lasers

Proceedings Papers

Study of Electroplated Compliant G-Helix Chip-to-Substrate Interconnects

Qi Zhu, Lunyu Ma, Suresh K. Sitaraman

Proc. ASME. InterPACK2003, 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2, 875-886, July 6–11, 2003

Paper No: IPACK2003-35342

DOI: https://doi.org/10.1115/IPACK2003-35342

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Topics: Diluents, Displacement, Electroplating, Geometry, Integrated circuit fabrication, Manufacturing, Microelectromechanical systems, Optimization, Packaging, Photolithography

NARROW

Improvement of the Reliability of Thin-Film Interconnections Based on the Control of the Crystallinity of the Thin Films

Evaluation of the Crystallographic Quality of Electroplated Copper Thin-Film Interconnection Embedded in a Si Substrate

Effect of Crystallographic Quality of Grain Boundaries on Both Mechanical and Electrical Properties of Electroplated Copper Thin Film Interconnections

Stress-Induced and Electro-Migration of Electroplated Copper Thin Film Interconnections Used for 3D Integration

Micro Texture Dependence of Mechanical Properties of Electroplated Copper Thin Films Used for Thin Film Interconnection

High-Density Room-Temperature 3D Chip-Stacking Using Mechanical Caulking With Compliant Bump and Through-Hole-Electrode

Micro Texture-Induced Variation of Mechanical Properties of Electroplated Copper Thin Films

Intermetallic Effects of Electroplated Lead-Free Solder Bumps Using a Novel Single Chamber Electroplating Process for Large Diameter Wafers

A Paradigm Shift in the Development of Chemical Mechanical Polishing (CMP): Cost-Effective CMP Planarization in Next Generation Substrate/Package Design and Manufacturing

A Chip-Scale Cooling Scheme With Integrated Heat Sink and Thermal-Fluidic I/O Interconnects

SOP Embedded Thin Film Resistors on High and Low Loss Thin Film Dielectrics

Wafer-Level Packaging Technology With Through-Hole Interconnections in Silicon Substrate

Evaluation of Surface Finish on Build Up Substrate

V-PAC: Vertical Packaging for Assembly-Compatible Chip Stacks

Study of Electroplated Compliant G-Helix Chip-to-Substrate Interconnects

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