In this paper, the study on failure mechanism of moisture sensitivity reliability is reported. It focuses on the PCT conditions which are 121°C, 2atm, 100RH%, and 168 hr. The general failure mode is delamination on the interface between die attach material and die backside. Interestingly, the delamination exists as a gap of 20∼40 μm. In addition, the paper discusses the relative materials influences — for example, the moisture uptake of mold compound systems and die backside surface property effects. The degradation of the die attach material was analyzed by Dynamic Mechanic Analysis (DMA). The delamination surfaces are analyzed by Scanning Electron Microscope (SEM), and Optical Microscope (OM). Furthermore, Scanning Acoustic Tomograph (SAT) through scanning results reveals that the mold compound formula affects the amount of moisture uptake, which obviously would affect the PCT reliability.
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December 2002
Technical Papers
Study on Failure Mechanism of PCT Reliability for BT Substrate Based CSP (Chip Scale Package)
C. L. Chung,
C. L. Chung
I-Shou University, Department of Materials Science and Engineering, 1, Section 1, Shiuecheng Rd., Dashu Shiang, Kaohsiung, Taiwan, R.O.C.
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James Fan,
James Fan
ChipMOS Technologies Inc. No. 5, Nan-Ko Rd. 7, Science-Based Industrial Park, Tainan, Taiwan, R.O.C.
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M. L. Huang,
M. L. Huang
ChipMOS Technologies Inc. No. 5, Nan-Ko Rd. 7, Science-Based Industrial Park, Tainan, Taiwan, R.O.C.
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F. J. Tsai
F. J. Tsai
ChipMOS Technologies Inc. No. 5, Nan-Ko Rd. 7, Science-Based Industrial Park, Tainan, Taiwan, R.O.C.
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C. L. Chung
I-Shou University, Department of Materials Science and Engineering, 1, Section 1, Shiuecheng Rd., Dashu Shiang, Kaohsiung, Taiwan, R.O.C.
James Fan
ChipMOS Technologies Inc. No. 5, Nan-Ko Rd. 7, Science-Based Industrial Park, Tainan, Taiwan, R.O.C.
M. L. Huang
ChipMOS Technologies Inc. No. 5, Nan-Ko Rd. 7, Science-Based Industrial Park, Tainan, Taiwan, R.O.C.
F. J. Tsai
ChipMOS Technologies Inc. No. 5, Nan-Ko Rd. 7, Science-Based Industrial Park, Tainan, Taiwan, R.O.C.
Contributed by the Electronic and Photonic Packaging Division and presented at Poly 2000, London, United Kingdom, December 4-5, 2000. Manuscript received at ASME Headquarters, May 2002. Guest Editor: Bernd Michel.
J. Electron. Packag. Dec 2002, 124(4): 334-339 (6 pages)
Published Online: December 12, 2002
Article history
Received:
May 1, 2002
Online:
December 12, 2002
Citation
Chung, C. L., Fan , J., Huang , M. L., and Tsai, F. J. (December 12, 2002). "Study on Failure Mechanism of PCT Reliability for BT Substrate Based CSP (Chip Scale Package) ." ASME. J. Electron. Packag. December 2002; 124(4): 334–339. https://doi.org/10.1115/1.1498265
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