High Gain and Wideband Antenna-in-Package Solution Using Fan-Out Technology

Antenna-in-package (AiP) has been widely applied with advantage of compact size, good performance, and relatively low cost. Conventional chip interconnection technologies used for AiP integration include wire bonding, flip-chip packaging, and fan-out wafer level packaging (FOWLP), among which fan out technology has smallest parasitic parameters with low insertion loss, and facilitates broadband design of millimeter wave system. Fan-out packaging is also widely adopted due to its high-density interconnection ability, with no separate substrate needed. One problem for AiP structures adopting fan-out technology such as embedded wafer level ball grid array (eWLB) is that the antenna is generally patterned on redistribution layer (RDL), which forms a two-dimensional integration [1–4]; antenna realization with large aperture requires a larger molding size, which not only adds to cost but also leads to warpage problem. For fan-out AiP, antenna patterned on RDL layers with epoxy molding compound (EMC) substrate also brings design inconvenience. Antenna with separate substrates can be embedded in EMC with more design flexibility [5], yet the structure in Ref. [5] is still two-dimensional. In comparison, for AiP topology adopting wire bonding or flip-chip packaging, the integration generally forms a more flexible three-dimensional stacked structures [6–8], where the antenna can be stacked on top of the microwave integrated circuit (MMIC) die, a large radiation array can be formed with more design freedom on feeding and antenna structures.

For large scale antenna array, substrate-integrated waveguide (SIW) can be used to reduce insertion loss of feeding path, and multilayer substrate is often applied to form the stacked SIW power divider. Low temperature cofired ceramic SIW is most widely used [9–11] with blind/buried vias. Organic substrate is also frequently adopted [12–14]. For the conventional printed circuit board (PCB) process, one method for organic substrate SIW is to fabricate multiple PCB boards separately and stack the manufactured layers together with conductive adhesive [12]. In Ref. [14] normal multilayer PCB process is adopted using two layers of RO4350 laminated with prepreg, coupled ground apertures are formed on the two sides of the prepreg bonding layer for signal transmission, with gain loss due to electromagnetic wave leakage into the bonding layer.

Basically, SIW slot radiates with a narrow bandwidth [15,16]. Various techniques have been adopted for bandwidth enhancement. In Ref. [13] normal PCB process is adopted with SIW slots coupled to patch array on top, large gain and wide bandwidth can be realized, reported bandwidth is 89.5–98 GHz for –10 dB return loss. Magneto-electric (ME) dipole is another wideband topology that is frequently used [15,17,18]. For ME dipole, aperture on SIW surface ground forms the magnetic dipole, patches with vias along two sides form electric dipole, coupling of two orthogonal sources creates a complementary radiation pattern with wide bandwidth. In our project, a modified ME dipole is proposed, the modified structure eliminates the blind-bury via problem when realized with normal PCB lamination process. A 60 GHz transceiver MMIC chip for digital communication is integrated, with required signal bandwidth of 55–65 GHz.

The SIW antenna is integrated to form a three-dimensional structure in our project, as shown in Fig. 1. The PCB SIW antenna is stacked onto the EMC package. With a larger SIW antenna area compared with the EMC package, relatively small molding size can be maintained along with a large radiation aperture and a high antenna gain. A right-angle transition PCB board is embedded in EMC to convert the signal from chip side to the backside of EMC, coupling design is adopted instead of via interconnection, which alleviates difficulties on design and fabrication at the interface between the stacked antenna and the right-angle feeding structure.

The paper is arranged as follows, antenna design is presented in Sec. 2; thermal and warpage performances are analyzed, fabrication processes are also discussed. Measurement results of the SIW antenna are described in Sec. 3; radiation performance of the AiP system is verified; a comparison with FOWLP AiPs in literature is also given out. Conclusions are presented in Sec. 4.

Conventional ME dipole structure is generally formed by at least two substrate layers, one layer for the SIW feeding network, and another layer for ME dipole radiation units. Via array is arranged in the ME dipole to connect the patches of ME dipole to the top ground surface of the SIW, as shown in Fig. 2. Blind-bury via problem exists when the structure is realized with low-cost multilayer PCB process. In this work a modified ME dipole is designed as illustrated in Fig. 3. A lower patch is inserted to form Stacked patches which are connected through vias. The inserted lower patch has width near λ/4, functions as a λ/4 open-circuit microstrip line (MS line), and forms a virtual short that connects the vias to the SIW surface. The structure is fabricated using two RO4350B core layers laminated with RO4450F prepreg, eliminating the blind-bury via problem. The thickness of core and prepreg layers are 0.5 mm and 0.2 mm, respectively, with dielectric constant of 3.66.

For further bandwidth enhancement, a matching via post is placed at the side of the radiation aperture in SIW as in Fig. 3, broadens the impedance bandwidth to 15 GHz from the originally 10 GHz if no via postis adopted. Simulation diagram in Fig. 4 includes a pair of ME dipoles driven by a SIW T-junction power divider. The simulation uses a waveguide port with no renormalization as the excitation source, placed at the SIW input. A via post is also arranged at the center of T-junction for impedance matching with distance d1 0.76 mm to SIW sidewall. The stacked patch size Wp × Lp is 0.58 mm × 2.3 mm; here patch width of 0.58 mm is near $λ/4$ length considering fringing effect. The radiation slot on SIW surface has a size Wa × La of 0.6 mm × 1.83 mm. SIW width W0 is 2.28 mm, sidewall via diameter and distance are 0.3 mm and 0.5 mm, respectively. Other sizes in Fig. 4 are d2 = 0.58 mm, W1 = 0.28 mm, W2 = 0.36 mm, W3 = 0.14 mm, and L = 6.6 mm. Simulated in-band input reflection coefficient is lower than –18 dB, with gain of 10.47 dB at 60 GHz, as shown in Fig. 5. Sidelobe exists on radiation pattern due to 4.21 mm center distance between the two radiation units, which is near one wavelength at 60 GHz.

The right-angle transition structure is shown in Fig. 6. Three waveports are arranged at the coplanar waveguide (CPW) line input and the two sides of the SIW, respectively. The input reflection coefficient is plotted at the CPW line waveport. Thickness of the molding compound is 500 μm. The right-angle transition board is fabricated using two RO4350B core layers with thickness of 170 μm and 100 μm, respectively, laminated by prepreg with thick 100 μm. An EMC layer of about 130 μm thickness is covered on top of the PCB board. For fan out technology, the RDL layer is formed by multipolyimide (PI) dielectric layers with single layer thickness of about 10 μm, and the total PI thickness is around 30 μm. Since it is unable to planarize the PCB metal layer with thickness higher than 0.5 oz, no metallization is formed on bottom PCB surface in this work.

Similar to ME dipole mentioned above, stacked patches are also adopted in the right-angle transition structure. As shown in Fig. 6(b), the stacked patches are formed on the embedded right-angle transition PCB board, coupling the SIW input slot on the upper side to the ground aperture on the lower side; the ground aperture is also formed on the embedded PCB board. A MS line patterned on RDL metal layer is used to feed the ground aperture. For AiP integration, the RDL MS line connects to ground-signal-ground chip pad through the CPW, as in Fig. 6(a). Two radial stubs are adopted for termination of CPW ground on RDL layer, forming virtual interconnection between the RDL CPW ground and the MS line ground in PCB. The size of the patches is 1.9 mm × 0.82 mm, the SIW feeding slot is 1.9 mm × 0.4 mm, ground aperture is 1.65 mm × 0.35 mm, radius of the stub is 0.76 mm. Other sizes in Fig. 6(a) are Ws = 0.1 mm, W1 = 0.4 mm, W2 = 0.9 mm, Ls = 0.66 mm. $λ/2$ tapered MS line is inserted for impedance matching as shown in Fig. 6(a). The simulation results are illustrated in Fig. 7; a wideband input matching is realized. In-band insertion loss from CPW to SIW dual output is better than –4.1 dB, which is equivalent to a total transmission loss of –1.1 dB, including the transition loss at the junction interface between the MS line and the CPW line.

The whole 4 × 4 SIW antenna array is shown in Fig. 8. A waveport is placed at the input of CPW line with port impedance 50 Ω. The CPW ground formed on RDL layer should be patterned carefully at the region overlapping the PCB ground, especially at the two sides of radial stubs. Simulation shows a wide input impedance bandwidth as in Fig. 9. Realized gain is 14.46 dBi under 60 GHz including loss of CPW feed line with length 3 mm, which is near equal to the feeding length on AiP RDL layout.

Considering the thickness fluctuation of the PCB cores and the EMC, simulation is performed under modified thicknesses, which are increased or reduced by 10%. The thickness modifications include the two PCB cores of the embedded board (increase or decrease simultaneously), the two PCB cores of the SIW antenna board (increase or decrease simultaneously), and the EMC. Calculated thickness of the EMC layer on top of the embedded PCB board varies from 53 μm to 207 μm. Figure 10 shows the simulated results. The input reflection coefficients are below –10 dB under most conditions; in-band gains are larger than 12 dBi with no destructive gain loss observed. The SIW antenna is then checked by measurements in the anechoic chamber.

Thermal simulation is performed with ansys, as shown in Fig. 11. The four metal layers of the SIW antenna have copper area of 99.8%, 95.2%, 11.7%, and 11.7% over the total antenna area; the first two copper layers are included in simulation with thickness 35 μm each. Aluminum heat sink with contact area of 31 × 31 mm² is mounted on the backside of AiP function board. Material thermal conductivities adopted are150 W/(m·°C) for silicon, 1 W/(m·°C) for EMC, 67 W/(m·°C) for solder ball, 0.69 W/(m·°C) for transition PCB board, 0.38 W/(m·°C) (XY direction) and 0.3 W/(m·°C) (Z direction) for test board, 164 W/(m·°C) for aluminum heat sink, and 400 W/(m·°C) for copper ground on test board and SIW antenna. Heat transfer coefficient to the ambient air is set between 3 and 8 W/(m²·° C). Ambient temperature is 22 °C. Simulation shows for chip power of 0.5 W/mm³ which is calculated to be 0.558 W, and 1 W/mm³ which is 1.12 W, the junction temperatures are 64 °C and 105 °C, respectively, as shown in Table 1. For power consumption of 0.558 W, the aluminum heat sink can be omitted with simulated junction temperature of 77 °C. Thus the AiP system can work properly with no heat sink needed for chip power around 0.5 W. Simulated chip-environment thermal resistance is about 75 °C/W and 100 °C/W with and without aluminum heat sink, respectively.

The SIW antenna itself has large thermal resistance to the ambient air, which is about 550 °C/W for antenna area of 366 mm², assuming a heat transfer coefficient of 5 W/(m²°C). Heat conduction enhancement is brought by the SIW copper ground plane, which helps to build up the thermal field on the EMC body [19]; heat is conducted through the SIW copper layer and distributed evenly on the EMC body, forming a lower temperature gradient around the MMIC die [19]. Heat dissipation is improved along the path from EMC through the PCB board into the air, and the junction-environment thermal impedance is reduced. Further improvement can be acquired by adding thermal vias, increasing copper ground thickness on test PCB board, and inserting copper thermal conductive pad between the MMIC chip and the SIW antenna copper ground [19]. Application of EMC material with higher thermal conductivity and lower coefficient of thermal expansion (CTE) is also an attractive research direction, yet certain process stability problems remain to be solved. The design is verified by temperature measurement on the surface of SIW antenna and the backside of test board, as shown in Fig. 11.

Warpage of the fan-out BGA package is caused by thermal expansion mismatch of the materials in package, chemical shrinkage of the EMC, and other process factors. Warpage should be considered at room temperature and reflow soldering temperature, the latter causes deviation of solder bump array from planarity with respect to the seating PCB plane, gives rise to open-circuit failure. In our project, the SIW antenna is attached onto the AiP BGA package after the BGA package has been mounted onto the PCB test board, and only the warpage of AiP BGA package is considered.

For liquid molding compound adopted in eWLB technology, the EMC curing process includes compression molding cure (CMC) and the subsequent postmolding cure (PMC). Warpage caused by chemical shrinkage is relaxed by the effect of the viscoelastic behavior. During CMC process, the volume shrinkage is a function of pressure, temperature, and degree of cure (DOC). After the CMC process, the degree of cure of molding compound is near to gel point when the mechanical stiffness starts to develop. During the following PMC process, chemical shrinkage induces stress and warpage, which is mitigated by viscoelastic relaxation behavior. In our work, the chemical shrinkage is not considered, which may cause no large simulation error if low chemical shrinkage EMC is used [20]; only effect of thermal expansion mismatch is considered, and the elastic EMC model is used. This simplified assumption may lead to larger simulated warpage value [20], yet still provides some basic insights on manufacturing feasibility.

The heterogeneous integrated structure used in ansys warpage simulation is shown in Fig. 12. Adopted material parameters are listed in Table 2. RO4350B is the glass reinforced hydrocarbon/ceramic material of thermoset resin system with glass transition temperature (Tg) larger than 280 °C, which is helpful to maintain CTE and elastic modulus value with low variation at high temperature, and is assumed unchanged under reflow temperature. The room temperature is set to be 27 °C. The Pb-free solder ball adopted in our project is Sn96.5Ag3Cu0.5 with melting point of 217 °C, and the reflow temperature used in simulation is 240 °C. The PMC temperature is set as stress free temperature during simulation.

Thicknesses of the PI layer, MMIC die and the embedded PCB board are 30 μm, 170 μm, and 370 μm, respectively. The copper area of the four metal layers on the embedded PCB board has the ratio of 0%, 96.3%, 20%, and 20% over the PCB area, respectively. For simplicity, only the 96.3% copper plane is included in simulation.

The simulated warpage under room temperature and reflow temperature is 40 μm and 23.9 μm, respectively, as in Fig. 13. The warpage level is low as the size of the embedded PCB board is 4 mm × 3.9 mm which is relatively small. The heterogeneous integration shows no severe warpage increasing compared with conventional single MMIC die integration. In fact, at reflow temperature, the maximum deformation appears at the MMIC die location since the CTE mismatch between the MMIC die and EMC is higher than the mismatch between the PCB board and EMC.

Simulation also shows the warpage increases as the EMC thickness reduces. Generally, an EMC thickness as low as 300 μm adds to difficulties as this will lead to a large warpage at room temperature; the low EMC elastic modulus under reflow temperature with thin EMC also causes large fluctuation of simulated warpage result with various parameter settings. In our design, the EMC thickness is 500 μm, which is in the range of commonly adopted process thickness.

The miniature right-angle transition board and MMIC die are integrated using fan-out chip-first technology. The trace width/space design rule for RDL metallization is 30 μm/30 μm which is relatively loose in order to tolerate surface flatness fluctuations of the reconstituted wafer. Dual RDL metallization layers are adopted for signal routing. A third layer of under bump metallization is used for solder bumping.

The MMIC chip and the miniature PCB board are first molded in the 12-in. reconfigured wafer. The temporary carrier is made of stainless steel. The chip and the miniature PCB board are picked-and-placed onto the carrier after the thermoreleased tape is attached to carrier surface. Liquid molding compound is dispensed and compressed homogeneously to form the reconstituted wafer with thickness of 700 μm under vacuum condition and 125 °C, the pressure is 250 kN and the speed is controlled slow enough to avoid die shift. The liquid molding compound has low chemical shrinkage and its thermomechanical characters match with carrier to reduce stress-induced die shift and warpage caused by molding process. Postmold curing is done at 150 °C for 60 min.

After molding the whole wafer is peeled off from the temporary carrier, and the wafer is annealed to reduce warpage. RDL layers are then formed on the surface; photo-imaginable dielectric solution is spin-coated onto the wafer followed by soft bake on hot-plate at 120 °C for 4 min, via hole is patterned by exposure using UV i-line for 30 s. After post exposure, the reconstituted wafer was developed by commercial solvent and cured at 230 °C for 4 h under N₂ atmosphere.

After via patterning, a Ti/Cu seed layer with thickness of 500 nm is sputtering deposited onto the photo-imaginable dielectric surface, with Ti layer adopted to increase interfacial adhesion. Thickness of Ti layer should be appropriate to avoid discontinuous Ti distribution on surface, which may cause delamination at interface region. After Ti/Cu sputtering, a layer of photo-resist is spin-coated, followed by photo-etching. Cu plating is then carried out with thickness 5 μm. Finally, photo-resist is stripped off and the exposed seed-layer is wet-etched, completing the wire patterning of the first RDL layer. After repetition process of the dual RDL layers, a third under bump metallization layer is formed. Finally, the wafer is grinded and diced, the molding thickness is thinned to 500 μm. The diameter of mounted solder ball is 400 μm. The process for the heterogenous integration is verified by a reference run before manufacturing, with interface profile checked by the scanning electron microscope.

The AiP fan-out BGA package is manufactured in Zhongwei High-tech Electronics Co. Ltd. in Wuxi, Jiangsu, China. The BGA package is mounted onto test board. The SIW antenna is then attached onto the top surface of AiP BGA package by adhesive in the package laboratory in Tsinghua. Metal pattern on embedded PCB board is adopted for SIW antenna alignment during assembly. The whole process is illustrated in Fig. 14. The manufactured AiP test board is checked with FeinFocus Y-Cougar X-ray imaging system. Radiation performance of the AiP module is measured with the Keysight N9041B UXA spectrum analyzer connecting to the standard horn antenna, which receives the mm-wave signal transmitted by the AiP.

The SIW antenna test board is shown in Fig. 15. For measurement setup, the right-angle transition pattern is formed on the test board, with another 200 μm thick PCB layer laminated on top to substitute the 130 μm EMC layer in the AiP module. The SIW antenna is attached to the test board using conductive silver paste. The microstrip feeding line of the transition structure is converted to CPW line, and a 1.85 mm coaxial connector is mounted. A back-to-back calibration structure contains the whole feeding path is also designed on the test board.

Measured antenna performance is shown in Fig. 16. Input reflection coefficient is lower than –10 dB in 55–65 GHz range. Insertion loss of the feeding path is –2.75 dB, according to back-to-back structure measurement results; the antenna gain is 15.2/14.0/15.6 dBi at 55/60/65 GHz after feeding loss cancelation. Measured and simulated radiation patterns for E-plane and H-plane under 60 GHz are shown in Fig. 17.

The MMIC and the small transition PCB board are integrated with conventional eWLB technology. The glass transition temperature of RO4350B is 280 °C, maximum process temperature is 230 °C during RDL polyimide dielectric curing, thus there is no temperature incompatibility. The integration process is checked by a reference run, Fig. 18 shows the resulted interface between RO4350B substrate and the EMC, covered by PI layer, with the sputtering metallization seed layer on top surface. The interface between PCB board, PI, and EMC shows good adhesion with no delamination. Measured step height is around 8 μm which is readily flattened by PI layer.

Manufactured BGA module is shown in Fig. 19. The EMC size is 10.4 mm × 12.9 mm, solder pad size is 330 μm. Package X-ray diagram is shown in Fig. 20 with embedded transition board at the lower left region. The step coverage image of metal line crossing the interface between EMC and embedded PCB board is displayed on the left. Feeding MS line displacement can be observed at the center of aperture, which is caused by alignment error during pick-and-place onto temporary carrier, and die shift during compression molding. Size and thickness differences between the miniature PCB board and MMIC chip may cause different position shift during compression molding. Simulation shows this displacement has little impact on aperture coupling performance.

The completed test board with AiP module mounted is shown in Fig. 21. Figure 22 displays the X-ray diagram; the solder array appears a uniform bump size. As no sufficient fabricated samples are available, the warpage of the BGA is not measured. The whole AiP test board is measured with good performance, which shows that the warpage is within normal range.

The system measurement is performed as in Fig. 23, control words are written into AiP MMIC chip on test board through serial peripheral interface, mm-wave signal transmitted by AiP is received using the horn antenna which connects to spectrum analyzer. Receiving power at 60 GHz is –37.8 dBm and –41.4 dBm with transmission distance 0.5 m and 1 m, respectively, which is –28.8 dBm and –32.4 dBm after calibrated by 9 dB cable loss. The Friis transmission equation is adopted for measured results evaluation. With the gain of SIW antenna and receive horn 14 dBi and 17.5 dBi each, calculated transmitting power of the AiP is 1.7 dBm and 4.1 dBm under distance 0.5 m and 1 m, the error is mainly caused by noise fluctuation and the imperfect test environment. Transmitted power delivered by chip power amplifier is 7 dBm, thus calculated total feeding losses from MMIC output to AiP antenna are 5.3 dB and 2.9 dB regarding the two distances.

Temperature measurement is performed with handheld thermometer, the MMIC has low power consumption of 340 mW, thus no aluminum heat sink is needed. Simulated maximum temperature point is 44 °C on SIW antenna surface, and 40 °C on the back surface of test PCB at the spot below MMIC chip. Measured temperatures at the two locations are 35.5 °C and 31 °C, respectively. The discrepancies between simulation and measurement are within 10 °C, which shows a meaningful simulation result; the error comes from the inaccuracy of the geometric model and the material parameters used in simulation. The junction temperature of the MMIC chip is 56 °C according to simulation.

Table 3 lists some FOWLP antenna-in-packages in the literature. Although various fan-out technologies are available, such as integrated fan-out wafer level packaging (InFO) and silicon wafer integrated fan-out technology, the eWLB technology remains the mostly adopted type for AiP system integration. For the InFO technology, grinding is adopted for planarization of EMC to expose the die contact pads; influence of warpage and surface flatness brings challenges to RDL process. Mass production yield is not sufficiently well, and the cost is relatively high. For die last technology such as silicon wafer integrated fan-out technology, process control for excessive silicon substrate removal from RDL carrier might be nontrivial. For eWLB technology, although there exist warpage and die-shift problems, the mature process provides an eligible solution with relatively low cost and low technical difficulties.

For AiP adopting fan-out technology, the integrated antenna gain is generally not more than 10 dBi due to limited package size, as can be seen in Table 3. For eWLB technology, 50 Ω MS line is unavailable for feeding line patterned on RDL layers, which brings difficulties to antenna array design. Large gain can be acquired using lens mounted on top, as in Refs. [3] and [24], the gain increases from 8 - 10 dBi to 25 dBi in Ref. [3], and from 5.9 dBi to 13.7 dBi in Ref. [24] with the lens mounted. In our work, SIW antenna is integrated with three-dimensional structure using eWLB packaging, a relatively high gain is acquired which is 14 dBi at 60 GHz with a 4 × 4 SIW radiation array. Measured bandwidth under –10 dB S11 exceeds the required band of 55–65 GHz, which is 50.3–70.8 GHz according to simulation. For fan-out AiP systems, thermal design is generally not considered in most literatures. A heat dissipation scheme is shown in Ref. [21] presented in year 2021. In our work, the SIW antenna not only brings gain enhancement but also improves heat dissipation, which can work with chip power of about 0.5 W, without needs of extra thermal design.

A three-dimensional antenna-in-package solution using FOWLP technology is proposed in this work. Modified ME dipole is adopted for radiation bandwidth enhancement of the SIW slot. A miniature PCB board is embedded in EMC for right-angle signal transition. Both embedded PCB board and the SIW 4 × 4 array antenna are fabricated by conventional PCB lamination processes. Measured results of the SIW antenna are consistent with simulation; realized bandwidth exceeds 55–65 GHz with in-band gain of 13.7–16.2 dBi. The AiP module is tested with well-functioned radiation performance. The SIW antenna also enhances thermal conduction, simulated junction temperature is 77 °C with chip power consumption of 0.558 W, and no extra thermal design is needed. Temperature measurement on sample surface is in agreement with simulation results. The proposed three-dimensional structure provides a high gain and wide band solution for AiP integration with low warpage brought by relatively small fan-out EMC package.

The authors attest that all data for this study are included in the paper.